1. Field of the Invention
The present invention relates to a method for forming a non-volatile memory cell and, more particularly, to a method for forming a non-volatile memory cell, which has a select transistor and a memory transistor, that eliminates substrate trenching during the etch step that initially defines the gate of the select transistor and the stacked gate of the memory transistor.
2. Description of the Related Art
A non-volatile memory cell is a semiconductor device that stores information even after power has been removed from the device. Two of the most common types of non-volatile memory cells are electrically-erasable programmable read-only-memory (EEPROM) cells and flash memory cells.
Historically, EEPROM cells differed from flash memory cells in that EEPROM cells utilize a select transistor to isolate the memory transistor from the drain line. Flash cells, on the other hand, do not use a select transistor. As a result, the memory transistor of a flash cell is directly connected to the drain line.
In addition, EEPROM cells typically have a thick layer of gate oxide which is formed over the channel regions of the select and memory transistors, and a thin layer of tunnel oxide which is formed over the drain region of the memory transistor. In contrast, the memory transistor in a flash cell typically has a thin layer of tunnel oxide which is formed over the entire channel region.
More recently, however, these distinctions have become blurred with the fabrication of hybrid memory cells which utilize an EEPROM select transistor in combination with a flash memory transistor. FIG. 1 shows a cross-sectional diagram that illustrates a conventional hybrid memory cell 100.
As shown in FIG. 1, cell 100 includes an EEPROM select transistor 110 and a flash memory transistor 120 which are both formed on a substrate 112. As further shown in FIG. 1, select transistor 110 includes a channel region 114 which is defined in substrate 112, a thick layer of gate oxide 116 which is formed over channel region 114, and a gate 118 which is formed over gate oxide layer 116.
Flash memory transistor 120, in turn, includes a channel region 122 which is defined in substrate 112, and a thin layer of tunnel oxide 124 which is formed over channel region 122. In addition, memory transistor 120 also includes a stacked gate 126 that has a floating gate 130 which is formed on oxide layer 124, an oxide-nitride-oxide (ONO) interpoly dielectric 132 which is formed on gate 130, and a control gate 134 which is formed on interpoly dielectric 132.
One problem with cell 100 is that it is difficult to fabricate a cell which has two different oxide thicknesses, thick gate oxide layer 116 and thin tunnel oxide layer 124, without severely trenching substrate 112 during the etch step that initially defines gate 118 of select transistor 110 and stacked gate 126 of flash memory transistor 120.
FIGS. 2A-2D show cross-sectional drawings that illustrate a conventional process for forming hybrid cell 100. As shown in FIG. 2A, the prior art process, which is described with respect to a 0.25-micron photolithographic process, begins with the formation of a layer of tunnel oxide 212 on a p-type substrate 210. Next, a first layer of polysilicon (poly-1) 214 is formed on tunnel oxide layer 212. Poly-1 layer 214, which is utilized to form floating gate 130, is then doped.
Once poly-1 layer 214 has been formed and doped, a first layer of oxide 216 is formed over poly-1 layer 214, followed by the deposition of an overlying layer of nitride 218. Oxide layer 216 and nitride layer 218 form the first two layers of interpoly dielectric 132.
Next, a first mask 220 is formed and patterned on nitride layer 218 to define an unmasked area on the surface of nitride layer 218. The unmasked area, in turn, defines an etch area on the surface of tunnel oxide layer 212.
After this, as shown in FIG. 2B, the unmasked areas of nitride layer 218, oxide layer 216, and poly-1 layer 214 are anisotropically etched until poly-1 layer 214 has been completely removed from the etch area on the surface of tunnel oxide layer 212. Following the etch, mask 220 is removed, and the portion of tunnel oxide layer 212 that was exposed by the etch is removed by a wet etch.
Next, as shown in FIG. 2C, a second layer of oxide 224 is formed over nitride layer 218, substrate 210, and the sidewalls of poly-1 layer 214. Second oxide layer 224 is utilized to form the third layer of interpoly dielectric 132. Following this, a layer of gate oxide 226 is formed over the surface of substrate 210 by thermal oxidation. In addition to forming gate oxide layer 226, the thermal oxidation step also densifies second oxide layer 224, and increases the thickness of the oxide formed on the sidewalls of poly-1 layer 214.
Once gate oxide layer 226 has been formed, a second layer of polysilicon (poly-2) 230 is deposited over oxide layer 224 and gate oxide layer 226. Poly-2 layer 230, which is utilized to form gate 118 and control gate 134, is then doped. (Optionally, a layer of metal silicide may be formed over poly-2 layer 230). Next, a second mask 232 is formed and patterned on poly-2 layer 230 (or the overlying metal silicide layer) to define a plurality of unmasked areas on the surface of poly-2 layer 230 (or the metal silicide layer). The unmasked areas, in turn, define a plurality of etch areas on the surface of tunnel oxide layer 212.
After this, as shown in FIG. 2D, the unmasked areas of poly-2 layer 230, oxide layer 224, nitride layer 218, oxide layer 216, poly-1 layer 214, and gate oxide layer 226 are anisotropically etched until poly-1 layer 214 has been completely removed from the etch areas on the surface of tunnel oxide layer 212.
However, as further shown in FIG. 2D, this etch step, which initially defines gate 118 of select transistor 110 and stacked gate 126 of memory transistor 120, severely trenches substrate 210 due to the differing step heights between transistors 110 and 120. This substrate trenching, in turn, is detrimental to the electrical performance of the memory cell.
Thus, there is a need for a process for forming a non-volatile memory cell that eliminates the substrate trenching that occurs during the etch step that initially defines the gate of the select transistor and the stacked gate of the memory transistor.
During the conventional fabrication of a non-volatile memory cell that has a select transistor and a memory transistor, the etch step that initially forms the gate of the select transistor and the stacked gate of the memory transistor undesirably etches away a significant portion of the substrate. The method of the present invention eliminates this substrate etching by forming the gate of the select transistor and the stacked gate of the memory transistor to have substantially the same step height. In addition, the step heights of the gate and the stacked gate are formed from a substantially identical combination of films.
The method of the present invention begins by forming a layered structure on a semiconductor material. The layered structure includes a first layer of insulation material which is formed on the semiconductor material, a first layer of conductive material which is formed on the first layer of insulation material, and a first portion of an interpoly dielectric which is formed on the first layer of conductive material.
After this, an opening in the layered structure is formed by removing a first portion of the layered structure. The opening has a width, and exposes the first layer of conductive material. Next, a cavity is formed in the layered structure by removing a second portion of the layered structure. The second portion of the layered structure, in turn, includes a portion of the first layer of conductive material. In addition, the cavity has a width which is greater than the width of the opening.
Following this, a second portion of the interpoly dielectric is formed on the first portion of the interpoly dielectric. Next, a second layer of insulation material is formed on the bottom surface of the cavity. The second layer of insulation material has a thickness such that the distance from the top surface of the semiconductor material to the top surface of the second layer of insulation material is greater than the distance from the top surface of the semiconductor material to the top surface of the first layer of insulation material.
Once the second layer of insulation material has been formed, a second layer of conductive material is formed on the second portion of the interpoly dielectric and the second layer of insulation material. The second layer of conductive material extends through the opening and fills up the cavity. After this, portions of the second layer of conductive material, the second portion of the interpoly dielectric, and the layered structure are selectively removed.
The above process initially forms the gate of a select transistor and the stacked gate of a memory transistor. The stacked gate includes the first layer of insulation material, and a floating gate which is formed on the first layer of insulation material from the first layer of conductive material.
The stacked gate of the memory transistor also includes an interpoly dielectric which is formed on the floating gate from the first and second portions of the interpoly dielectric, and a control gate which is formed on the interpoly dielectric from the second layer to conductive material.
The gate of the select transistor, in turn, includes the second layer of insulation material, and a gate which is formed on the second layer of insulation material from the second layer of conductive material. The gate of the select transistor has sidewalls, and the interpoly dielectric formed in the sidewalls.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings which set forth an illustrative embodiment in which the principals of the invention are utilized.